Automatic test pattern generation (“ATPG”) was developed to explicitly test each gate and path in an integrated circuit (“IC”) design. As ICs have become larger and more complex, the amount of logic to be tested per input/output test pin has increased dramatically, increasing test time and cost.
When an ATPG tool generates a scan test for a fault, or a set of faults, only a small percentage of scan cells in the scan channel need to take specific values (e.g., care bits). The rest of the cells in the scan channel are “don't care”, and are usually filled with random values. Relatively few bits in an ATPG generated test pattern are “care” bits.
Test Compression takes advantage of the small number of significant values (care bits) to reduce test data and test time. However, as Test Compression decreases channel lengths, the number of specified bits (e.g., care bits) per time slice increases. An ATPG process for a certain test pattern may specify certain bits (e.g., care bits) across multiple time slices of the test pattern in order to reduce toggling, and, therefore, power consumption. There can be a large variance in the number of care bits across time slices.
For a spreader network of a plurality of XOR logic gates (e.g., XOR decompressor), the maximum number of care bits that can be solved for each scan cycle is limited by the total number of scan inputs. Therefore, XOR decompressors cannot solve for slices that have more care bits than the available scan data (e.g., input variables). Further, XOR decompressors are also limited in that they are restricted to using only the scan data available in the same scan cycle.
Accordingly, there is a need for generating “extra” variables in the event the ATPG is presented with faults that require a much higher number of care-bits than can be supported efficiently by the current hardware (e.g., XOR decompressors).